ASIC Flow for Ibex base core in Arch Linux

I'll speed through setting up an ASIC synthesis flow for the Ibex RISC-V core using entirely open-source tools.

Tools

• Python 3.12.8 (for environment management)

• Yosys (logic synthesis)

• sv2v (SystemVerilog to Verilog conversion)

• OpenSTA (static timing analysis)

• OpenROAD-flow-scripts (for Nangate 45nm library files)

Step 1: Workspace Setup

Create a clean workspace:

mkdir workspace
cd workspace

Clone the Ibex repository:

git clone https://github.com/lowRISC/ibex.git
cd ibex

Set up a Python virtual environment:

python3 -m venv venv
source venv/bin/activate
pip install -r python-requirements.txt

Install the required tools (Arch Linux):

yay -S yosys sv2v opensta

Synthesis Configuration

Navigate to the ibex/syn directory and prepare the setup file:

cd syn
cp syn_setup.example.sh syn_setup.sh

We need the Nangate 45nm library. Clone OpenROAD-flow-scripts, alongside the ibex direcotry

cd ../..
git clone --depth=1 https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts.git

Find the library path:

cd OpenROAD-flow-scripts/flow/platforms/nangate45/lib
pwd

Edit syn_setup.sh to include:

export LR_SYNTH_CELL_LIBRARY_PATH=/your/path/OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib
export LR_SYNTH_CELL_LIBRARY_NAME=nangate

Make sure that the Library name NangateOpenCellLibrary_typical.lib is in the path

Running Synthesis

cd ~/workspace/ibex/syn
source syn_setup.sh
./syn_yosys.sh

You'll encounter this error:

../rtl/ibex_tracer.sv:743:7: Parse error: missing expected `end`

This occurs because the tracer contains debug code not meant for synthesis. Fix it by wrapping the problematic code in ibex/rtl/ibex_tracer.sv with: (the lines should span from around line number 737 to 767)

`ifndef SYNTHESIS
  // close output file for writing
  final begin
    if (file_handle != 32'h0) begin
      // This dance with "fh" is a bit silly. Some versions of Verilator treat a call of $fclose(xx)
      // as a blocking assignment to xx. They then complain about the mixture with that an the
      // non-blocking assignment we use when opening the file. The bug is fixed with recent versions
      // of Verilator, but this hack is probably worth it for now.
      static int fh = file_handle;
      $fclose(fh);
    end
  end

  // log execution
  always @(posedge clk_i) begin
    if (rvfi_valid && trace_log_enable) begin
      static int fh = file_handle;

      if (fh == 32'h0) begin
        static string file_name_base = "trace_core";
        void'($value$plusargs("ibex_tracer_file_base=%s", file_name_base));
        $sformat(file_name, "%s_%h.log", file_name_base, hart_id_i);

        $display("%m: Writing execution trace to %s", file_name);
        fh = $fopen(file_name, "w");
        file_handle <= fh;
        $fwrite(fh, "Time\tCycle\tPC\tInsn\tDecoded instruction\tRegister and memory contents\n");
      end

      printbuffer_dumpline(fh);
    end
  end
  `endif

Final Synthesis Run

./syn_yosys.sh

Successful synthesis will generate reports in with the date and time of the run

ibex/syn/syn_out/